In general, one critical property of an I/O buffer is the output edge-rate. If the edge-rate is too slow, the signal rise and fall time is too long, and thus, may not meet the frequency and timing requirement. On the other hand, as shown in FIG. 1, an edge-rate that is too fast may cause overshoot, undershoot, ring-back, and/or ledges that degrade signal integrity and may even cause functional errors in some circuits. Therefore, it is critical to keep the output edge-rate within a tightly controlled optimal range in order to meet the predetermined frequency and timing requirement and to ensure signal integrity.
FIG. 2 illustrates a typical output buffer in an existing semiconductor device. The I/O 200 includes a driver 210 and a pre-driver 220. The driver 210 includes a pull-up resistor 211 and an n-type Metal Oxide Semiconductor (NMOS) transistor 213 coupled in series between a voltage supply 209 and the ground. A pad 217 is also coupled to the node in between the pull-up resistor 211 and the nMOS transistor 213. The gate of the NMOS transistor 213, n_gate 215, is driven by the pre-driver 220. The pre-driver 220 includes a number of p-type Metal Oxide Semiconductor (pMOS) transistors 225 and a number of nMOS transistors 227. Based on two input signals to the pre-driver 220, namely slewp 221 and slewn 223, a corresponding number of pMOS transistors 225 and a corresponding number of nMOS transistors 227 are turned on to drive n_gate 215. The signals slewp 221 and slewn 223 are from an edge-rate compensation circuit.
Currently, one typical edge-rate compensation circuit employs an approach similar to resistance or impedance compensation. FIG. 3 illustrates an existing edge-rate compensation circuit 300. As shown in FIG. 3, by referencing an off-die resistor Rp 310, the compensation circuit 300 searches and locates a digital bit setting corresponding to the number of transistor legs of Mn 330 or Mp 320, whose resistance closely matches the resistance of Rp 310. The bit setting is then sent to the output buffer pre-driver 220 in FIG. 2 to turn on the same number of pMOS and NMOS transistors 225 and 227 in the pre-driver 220 as shown in FIG. 2. In this way, the pre-driver drive strength is compensated, and hence, the edge-rate of signals at the output buffer can be controlled.
One shortcoming of this approach is that the drive strength of the pre-driver 220 is not compensated according to the capacitance at the pre-driver 220 output and driver 210 input, n_gate 215. Thus, even though the capacitance at n_gate 215 may vary with process variation, voltage, and temperature (PVT), the pre-driver 220 drives n_gate 215 with the same strength across PVT. Therefore the edge-rate at the pad 217 varies with PVT. In some cases, this approach results in a +/−15% variation in edge-rate.
Another existing edge-rate compensation circuit utilizes an elaborate scheme which still infers the pad edge-rate based on the waveform applied to the gates of the pull-down n-type Field Effect Transistors (nFET) in the I/O driver. FIG. 4A illustrates such an edge-rate compensation circuit. Using the edge-rate compensation circuit 400, an edge-rate is determined by applying an M level staircase waveform to the pad 410. The M levels are triggered successively by some PVT compensated delay locked loop (DLL) stages 420 with a time interval of tr/N between the DLL stages 420. FIG. 4B shows the output waveform at the pad 410 with M=10 and N=9, with each of the DLL stages 420 changing the pad voltage by about 100 mV=(VTT−VOL)/N. Although the edge-rate compensation circuit 400 improves slew rate control, this implementation is expensive because the edge-rate compensation circuit 400 uses the DLL 430 and a constant external frequency source to gauge the time delay. Furthermore, as the shape of the output waveform 402 is non-linear as shown in FIG. 4B and the output waveform 402 depends on the load variation at the pad 410, the edge-rate variation is relatively large, causing excessive jitter.